[Patents] ABstracts to articles on hardware/software codesign

[Gregory Aharonian srctran@world.std.com]

    I have repeatedly referred to the existence of hardware/software
codesign tools as part of a basis for requiring that hardware and
software equally be patentable (or not patentable).  What follows are
abstracts to just a small fraction of the 1000+ papers in the last five
years on hardware/software codesign.  For most of what follows, you can
simply swap the occurences of "hardware" and "software", without changing
the meaning of any of these abstracts.

    For hardware/software, they both take similar amounts of time for
designing systems of the same complexity, they both can be automatically
designed by computers from a system specification, they both make use of
large libraries of reusable elements, they both have their industries
(which are converging), they both have open source offerings, they both
have been referred to as "technologies" for over thirty years, in light
of mathematical automata theory they are both equivalent expressions of
computing models, they both have non-physical features, they both have
expressional abstract protected by copyright and functional aspects
protected by patent, etc.  Electrons switched by a hardware circuit are
no more a physical transformation than electrons switched by software
which control switchable hardware.

    To allow patenting for one but not the other is to deny all of these
mathemtical, logical, technical and social equivalences.  And there is no
law that can survive serious intellectual challenge on either side of the
Atlantic that tries to treat them differently.

Greg Aharonian
                              ====================


    Page, I.; Dettmer, R.
    Software to silicon [hardware compilation].
    IEE Review, Sept. 2000, vol.46, (no.5):15-19.
Abstract:
    The principles of hardware compilation could be set to rewrite the
rule book of silicon design. This article describes Handel-C, a parallel
programming language that is providing programmers with a route to
FPGA-based VLSI design, not by offering them a familiar programming
environment combined with access to the parallel constructs familiar to
the hardware designer, but by expressing the parallelism at a totally
different level of abstraction; it doesn't describe the hardware like
an HDL does - it describes the computation.



    Endo, Y.; Koizumi, H.
    Hardware/software co-design method of ITS image processing development.
    Proceedings Seventh International Conference on Parallel and
       Distributed Systems: Workshops, 2000. p. 415-20.
Abstract:
    A hardware and software co-design method for the image processing
system of intelligent transport systems (ITS) is proposed. The objective
of this method is to optimize the division of functions between hardware
and software by the optimum tradeoff. In this method, the targeted overall
system is first modeled by software, and then functions and structures are
adjusted. The performance of each function of software and hardware in the
model is evaluated by simulation, and the optimized division of functions
between hardware and software is obtained. Each functionally divided
process of hardware and software is re-designed and fine-tuned and then
operations are verified by the co-design test board in order to quickly
design and construct a system which satisfies the design objectives. The
ITS image processing development area is chosen as an application example
for this method and its effectiveness is verified by evaluating the
construction of a safe driving support system.



    Re, M.; Salmeri, M.; Cardarilli, G.C.
    A CAD environment for fuzzy systems HW/SW mapping.
    2000 IEEE International Symposium on Circuits and Systems, p. 221-4 vol.4
Abstract:
    The new portable multimedia systems are characterized by very
low-power absorption, very high throughput, high complexity and shortened
time to market. In this kind of application, besides standard DSP
techniques, Intelligent Techniques(IT) such as Fuzzy Logic and Neural
Networks, are gaining more and more importance. This fact leads to the
development of new CAD tools for the optimization of the overall IT design
process. In this paper, a CAD environment named FSDT (Fuzzy System
Development Tool) is described. FSDT supports the different phases of the
development process namely optimization, simulation and code generation
either for software (C or Assembler) or hardware (Verilog) implementations
of Multiple Input Multiple Output (MIMO) fuzzy inference processors. FSDT
has been written in C++ and, at present, an implementation interfaced with
Matlab is available. A new implementation based on Ptolemy (a simulation
engine, developed at the University of California at Berkeley) is under
development.



    Carchiolo, V.; Malgeri, M.; Mangioni, G.
    Hardware/software synthesis of formal specifications in codesign of
        embedded systems.
    ACM Transactions on Design Automation of Electronic Systems,
        July 2000, vol.5, (no.3):399-432.
Abstract:
    CoDesign aims to integrate the design techniques of hardware and
software. In this work, we present a CoDesign methodology based on a
formal approach to embedded system specification. This methodology uses
the Templated T-LOTOS language to specify the system during all design
phases. Templated T-LOTOS is a formal language based on CCS and CSP
models. Using Templated T-LOTOS, a system can be specified by observing
the temporal ordering in which the events occur from the outside. In this
paper we focus on the synthesis of system specified by Templated T-LOTOS.
The proposed synthesis algorithm takes advantage of peculiarities of
templates T-LOTOS. Hardware modules are translated into a register
transfer-level language that manages some signals in order to drive
synchronization, while the software modules are translated into C using
to a finite state model whose operations are controlled by a scheduler.
The synthesis of the Templated T-LOTOS specification is based on the
direct translation of the language operators to ensure that the
implemented system is the same as the specified one.



    Gogniat, G.; Auguin, M.; Bianco, L.; Pegatoquet, A.
    A codesign back-end approach for embedded system design.
    ACM Transactions on Design Automation of Electronic Systems,
        July 2000, vol.5, (no.3):492-509.
Abstract:
    Continuous advances in processor and ASIC technologies enable the
integration of more and more complex embedded systems. Since their
implementations generally require the use of heterogeneous resources
(e.g., processor cores, ASICs) in one system with stringent design
constraints, the importance of hardware/software codesign methodologies
increases steadily. Interfacing heterogeneous hardware and software
components together through a communication structure is particularly
error prone and time consuming. Hence, on the basis of a generic
architecture dedicated to telecommunication and multimedia applications,
we propose an extended communication synthesis method that provides
characterization of communications and their implementation schemes in the
target architecture. This method takes place after the partitioning and
scheduling phase and may constitute the basis of a back-end of a codesign
framework leading to HW/SW integration.



    Noguera, J.; Badia, R.M.
    Run-time HW/SW codesign for discrete event systems using dynamically
        reconfigurable architectures.
    Proceedings 13th International Symposium on System Synthesis, 2000.
        p. 100-6.
Abstract:
    Hardware/software (HW/SW) codesign and reconfigurable computing (RC)
are commonly used methodologies for digital systems design. However, no
previous work has been carried out in order to define a run-time HW/SW
codesign methodology for dynamically reconfigurable architectures.
Besides, all previous approaches to RC context scheduling were based on
static scheduling techniques. In this paper, we present a run-time HW/SW
codesign methodology for discrete event systems using dynamically
reconfigurable architectures and a dynamic approach to RC multi-context
scheduling. We have applied our methodology to software acceleration and
present the obtained results.



    Muth, A.; Farber, G.
    SDL as a system level specification language for application-specific
        hardware in a rapid prototyping environment.
    IEEE Proc. 13th Int. Symposium on System Synthesis, 2000. p. 157-62.
Abstract:
    The specification of an embedded system at system level together with
co-joint hardware/software synthesis is a goal of many rapid prototyping
projects. SDL has been proposed as a formal and abstract specification
language well suited for this purpose. The implementation, of SDL's
asynchronous communication model in application specific hardware,
however, is unproportionally expensive in terms of area and response time.
This paper discusses the efficiency of the server model-the implementation
model used in all known codesign approaches based on SDL-and compares it
with an alternative implementation model for SDL known from software, the
activity thread model. In a combination of both implementation strategies,
the communication and synchronization overhead for each application can be
minimized, and an efficient implementation on distributed architectures
realized. The integration in an existing rapid prototyping design process
is presented as well as results gained from application examples.



    Kang, J.; van der Werf, A.; Lippens, P.
    Mapping array communication onto FIFO communication - towards an
        implementation.
    IEEE Proc. 13th Int. Symposium on System Synthesis, 2000. p. 207-13.
Abstract:
    In high-throughput real-time media processing systems, the
communication between processing units is typically specified as
multi-dimensional arrays. However, the implementation of such applications
is mostly FIFO (first-in, first-out) based. Mapping array communication
onto a FIFO-based implementation requires complex address generators if
the arrays have multiple dimensions. In this paper, we present a method
for mapping array communication onto an efficient microcomputer
architecture implementation based on FIFO communication via shared memory.
A good hardware/software partitioning for the address generation is
proposed. Furthermore, a complete design flow from specification to
implementation is described. We illustrate this method with a design case:
the communication of video frames between the front-end and the compressor
in an MPEG encoder.



    Ramanathan, D.; Roth, R.; Gupta, R.
    Interfacing hardware and software using C++ class libraries.
    IEEE Proc. 2000 Int. Conference on Computer Design, 2000. p. 445-50.
Abstract:
    As chip capacity increases and system-on-a-chip becomes more than
just a catch phrase, hardware and system design are being driven in new
directions. Systems are designed not just as hardware, but as a tightly
coupled combination of both hardware and software. C++, extended with
class libraries, is emerging as the way to design such complex systems.
This paper proposes methods to specify and refine designs from a purely
software description at a functional level to a level where the hardware
components are encapsulated as objects and their interfaces clearly
defined. The entire system functionality is described in C++ using some of
the commercially available class libraries like SystemC from Synopsys and
Cynlib from CynApps. We propose a methodology where a designer can migrate
software functionality. We also show that the software driver for the
hardware device is generated as a side-effect of the interface refinement
process. We demonstrate our methodology on the design of a fax machine
from a purely software description of the system. We refine the design by
implementing its decoder functionality in hardware and interfacing it with
the software encoder.


    Govindarajan, R.; Altman, E.R.; Gao, G.R.
    A theory for software-hardware co-scheduling for ASIPs and embedded
        processors.
    Proc. IEEE International Conference on Application-Specific
        Systems, Architectures, and Processors, 2000, p. 329-38.
Abstract:
    Exploiting instruction-level parallelism (ILP) is extremely important
for achieving high performance in application specific instruction set
processors (ASIPs) and embedded processors. Existing techniques deal with
either scheduling hardware pipelines to obtain higher throughput or
software pipeline-an instruction scheduling technique for iterative
computation-loops for exploiting greater ILP. We integrate these
techniques to co-schedule hardware and software pipelines to achieve
greater instruction throughput. In this paper, we develop the underlying
theory of co-scheduling, called the Modulo-Scheduled Pipeline (or
MS-Pipeline) theory. More specifically, we establish the necessary and
sufficient condition for achieving the maximum throughput in a given
pipeline operating under module scheduling. Further, we establish a
sufficient condition to achieve a specified throughput, based on which we
also develop a methodology for designing the hardware pipelines that
achieve such a throughput.



    Auguin, M.; Bianco, L.; Capella, L.; Gresset, E.
    Partitioning conditional data flow graphs for embedded system design.
    Proc. IEEE International Conference on Application-Specific
        Systems, Architectures, and Processors, 2000. p. 339-48.
Abstract:
    The complexity of embedded applications increases continuously.
Integration advances provides a rising range of possibilities to implement
a system on a chip. The designers are faced to the difficult challenge to
select the right units to implement the application functionalities so
that the silicon area is minimized and the time constraints of the
application are met. This paper presents an effective method to design
system architectures which operates on a conditional data flow graph which
is well suited to represent signal processing applications.



    Lavagno, L.; Pino, B.; Reyneri, L.M.; Serra, A.
    A Simulink(c)-based approach to system level design and architecture
        selection.
    IEEE Proc. of the 26th Euromicro Conference. 2000, p. 76-83 vol.1.
Abstract:
    We propose a design flow for low-power and low-cost, data-dominated,
embedded systems which tightly integrate different technologies and
architectures. We use Mathworks' Simulink(c) environment for functional
specification and analysis of performance criteria such as timing (latency
and throughput) and power dissipation. The flow can exploit trade-offs
between software and hardware as well as between digital and analog
implementations, and it can generate, respectively, the C, VHDL and Skill
codes of the selected architecture. The proposed system has several cost
functions such as power consumption, speed, area, and it can optimize the
design according to any of them.



    Drechsler, R.; Drechsler, N.; Mackensen, E.; Schubert, T.; and others.
    Design reuse by modularity: a scalable dynamical (re)configurable
        multiprocessor system.
    IEEE Proc. of the 26th Euromicro Conference. 2000, p. 425-31 vol.1.
Abstract:
    We present a scalable, low cost multiprocessor system, which is used
in the area of measurement, regulation, controlling and soft computing.
The system is an example of extremely modular hardware/software design.
Modular in this context means that we can easily change or optimize
individually the components in the system for a given problem. One of the
most important aspects of our multiprocessor system is the fact that the
user can dynamically change the communication topology by software
'on-the-fly'. Thus, the hardware can be (re)configured during operation in
less than 1 ms. By this, the CPUs in the multiprocessor system can
communicate directly without any invention of another processor preventing
the typical bottleneck in parallel systems. First applications have been
implemented in an embedded controller for a vote counting machine, with
emphasis on high data security and high throughput.



    Schlebusch, H.-J.
    SystemC based hardware synthesis becomes reality.
    IEEE Proc. of the 26th Euromicro Conference. 2000, p. 434 vol.1.
Abstract:
    Summary form only given. The advances in ASIC technology have enabled
the design of systems-on-chip (SoC). The complexity associated with SoC is
creating many new challenges at all levels of the design process. The
article discusses SystemC, an open community C++ modeling platform for
system-level design and hardware/software co-design. SystemC is broadly
supported by a large and growing number of leading system houses,
semiconductor companies, intellectual property (IP) providers, embedded
systems and EDA tool vendors through the Open SystemC Initiative (OSCI).
The objective of the OSCI is to engender a whole new market for
system-level design solutions, based on its support of SystemC and a
common modeling platform with built-in interoperability. In order to gain
acceptance from the SoC engineering community, the new standard modeling
platform has to be more than just a means of communication; it has to
support all kinds of features that can help to solve their most burning
issue, namely "time-to-market". For SoC, it is essential to support the
reuse of intellectual property (IP) for multiple designs. That in turn
means the support of IP creation as well as IP integration. Until
recently, the synthesis tools required VHDL/Verilog descriptions as the
design entry language, which of course was one good reason for hardware
engineers not to adopt SystemC in their design flow. In June 2000,
Synopsys introduced SystemC Compiler, a synthesis tool that allows one to
synthesise hardware IP from a synthesizable subset of SystemC, thereby
removing one of the biggest hurdles for the adoption of SystemC by the
hardware design community.



    Kawarabayashi, M.; Jin-Qin Lu; Goto, K.; Fung, P.W.
    System level design methodology for system on a chip.
    NEC Research and Development, July 2000, vol.41, (no.3):248-52.
Abstract:
    Though the size of system on a chip (SoC) will increase to more than
30-million gates by 2002, their design productivity cannot be improved
with conventional Electronic Design Automation (EDA) technologies.
Intellectual Property (IP) based or platform based design is the right
direction for increasingly sophisticated SoCs. NEC Electronics, Inc. is
proposing a new SoC design environment to raise design productivity.
Because system level design is now one of the most immature phases of SoC
design, we focus on both hardware (HW) and software (SW) design before
Register Transfer Level (RTL) design. HW/SW co-design is the key
technology in system level design; however present tool capabilities
are not adequate to satisfy today's designers. This paper describes an
efficient solution with a combination of new EDA technologies in
system analysis, HW/SW co-design, HW design/verification, and SW
design/verification as well as appropriate IP models for each design
phase.



    Yanbing Li; Callahan, T.; Harr, R.; Kurkure, U.; and others.
    Hardware-software co-design of embedded reconfigurable architectures.
    IEEE 2000 Design Automation Conference, p. 507-12.
Abstract:
    The authors describe a novel hardware/software partitioning approach
for embedded reconfigurable architectures consisting of a general-purpose
processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and
a memory hierarchy. We have developed a framework called Nimble that
automatically compiles system-level applications specified in C to
executables on the target platform. A key component of this framework is a
hardware/software partitioning algorithm that performs fine-grained
partitioning (at loop and basic-block levels) of an application to execute
on the combined CPU and datapath. The partitioning algorithm optimizes the
global application execution time, including the software and hardware
execution times, communication time and datapath reconfiguration time.
Experimental results on real applications show that our algorithm is
effective in rapidly finding close to optimal solutions.



    Pumo, J.
    SoC: the convergence point for solutions of the 21st Century
    IEEE Custom Integrated Circuits Conference, 2000. p. 1.
Abstract:
    Summary form only given. The future challenge from the customer is to
deliver a complete solution that meets system requirements function,
performance and price - in a competitive time-to-market. The answer: A
System-on-a-Chip (SoC). The term "SoC" defines a product that is targeted
for a specific application and contains an entire system, complete with
embedded software. SoC also defines a process which starts with system
requirements, which are modeled, analyzed and partitioned into hardware
and software for design and implementation. This process depends on four
capabilities which build upon one another to make SoC a reality. The first
capability, Manufacturing Technology, is the basic enabler for SoC.
Silicon processing, packaging and test technology are advancing rapidly to
accommodate the higher complexity of integrated systems. The complexities
afforded by the technology require a second capability, that of Silicon
Implementation. Silicon Implementation, the conversion of data from design
representation level to manufacturing formats, must be enhanced to deal
with the high device counts and mixed device types. Due to the discrepancy
between the complexity provided by the Manufacturing Technology and
delivered through Silicon Implementation, a third capability, Reusable IP
Portfolio, is required. The Reusable IP Portfolio provides a central
location for strategic blocks of IP which have been designed for reuse.
In order to identify and define strategic blocks to be placed in the
Portfolio, a fourth capability, System Design Skills, is needed. System
Design Skills provide the ability to work above the level of
hardware/software partitioning to define a complete system at a high
level representation where tradeoffs can be made most efficiently.